C(V) curves, which give the MOS capacitance as a function of the gate voltage, make it possible to determine characteristic dimensions of an MOS stack, such as in particular the gate oxide thickness given as silicon oxide equivalent, which is denoted EOT (Equivalent Oxide Thickness), and the flatband voltage (FBV) i.e. the voltage at which the valence and conduction bands in the semiconductor are flat.
These characteristic dimensions are used to characterize, monitor and compare electronic processes according to the recommendations established by the ITRS body (“International Technology Roadmap for Semiconductors”) in its roadmap. This roadmap, which assesses the progress of miniaturization (Moore's law) in technological generations referred to as “nodes”, associates characteristic dimensions with each node, these comprising in particular the gate oxide thickness as EOT.
The invention addresses the most advanced technological processes, for which the EOT is around one nanometre or even less.
For these nanometric processes, the characterization of MOS gate/oxide/semiconductor stacks requires that very precise curves be obtained, and then that the parameters of the stack (EOT, FBV, . . . ) be evaluated by models taking into account, in particular, quantum effects.
The C(V) curves of an MOS stack are conventionally obtained by means of a commercial impedance analyzer, for example the analyzer marketed under the name Agilent 4284A, which allows a complex impedance measurement to be carried out in the small-signal range (superposition of a small-signal voltage with a DC voltage).
For nanometric processes, these techniques of recording curves from conventional test structures do not allow the desired precision and reliability to be obtained, because numerous factors interfere with the impedance measurements.
Specifically, with surfaces measuring 100 microns by 100 microns which make it possible to obtain capacitances of the order of a few hundred picofarads (10−12 farads), the measurements are affected by the increase in leakage currents through the gate oxide due to the tunnel effect. It is known that the use of smaller MOS transistor surfaces, for example of the order of 10 microns by 10 microns, allows this problem of stray leakage current to be overcome by reducing the access resistances, as described for example in the publication by C. Leroux et al. “Characterization and modeling of nanometric SiO2 dielectrics” Microelectronic Engineering, Volume 72, Issues 1-4, April 2004, pages 121-124.
Owing to their lower capacitance value (picofarads), these structures with smaller dimensions are further affected by the relative increase in the stray capacitances, whether these are stray capacitances inherent to the MOS transistor structure or capacitances belonging to the measuring apparatus and interconnection capacitances between the structure to be tested and the measuring apparatus.
More precisely, three categories of stray capacitances are thus involved in the measurement. These are the stray capacitances induced by the MOS structure itself; the stray capacitances introduced by the interconnection lines joining the MOS structure to the test pads onto which the electrodes of the measuring apparatus will be placed; and the stray capacitances associated with the measuring apparatus.
FIGS. 1 and 2 illustrate the stray capacitances induced by an MOS transistor structure. An MOS transistor (FIG. 1) comprises an active transistor zone ZA in the substrate, on which a control gate G makes it possible to control a channel between the diffusion zones. The dimensions of a transistor are the dimensions of the channel: the length L of the channel, that is to say the longitudinal distance between the source and drain diffusion zones; and its width, which is the transverse length of the channel. These are the design lengths and widths on reticles for the fabrication of transistors. The surface area of the transistor is thus given by the product L·W. FIG. 2 shows the source diffusion zone S and the drain diffusion zone D, the gate G comprising a gate oxide gox arranged on the substrate over the channel zone cc, and the gate electrode ge on the gate oxide, as well as the spacers or insulators e1, e2 conventionally provided laterally on the sides of the gate.
The stray capacitances inherent to such an MOS transistor structure are the capacitances associated with the perimeter of the transistor. These are, as is well known:                the corner capacitances Ca1, Ca2, Ca3, Ca4 (FIG. 1) of three-dimensional nature, at the position of the four corners corresponding to the vertices of the gate zone G with dimensions W by L, which overhangs the active zone ZA;        the stray capacitances of the gate edge on the active zone, which comprise the capacitances Cw along its width W and the capacitances Cl along its length L. Referring to the example of the 45 nanometre technology node, these edge stray capacitances are of the order of 0.2 femtofarad (10−15 farad) per micrometre of width W or length L. The capacitances Cw comprise the capacitances via the spacers and the capacitances via the oxide, between the gate and the source and drain diffusion zones. It is this which is illustrated in FIG. 2: for the capacitances Cw along the width W, the stray capacitance c9 corresponds to the stack comprising the gate electrode ge/spacer e1/diffusion zone S; and the stray capacitance c10 corresponds to the stack comprising the gate electrode ge/gate oxide gox/diffusion zone S. The capacitances Cl are associated with the specific capacitances observed at the active zone edge.        
FIG. 3 illustrates the stray capacitances induced by the test pads provided on the semiconductor device, in order to receive the measurement tips (electrodes) of the measuring apparatus, and by the interconnection lines, typically aluminium lines, which allow the gate and the source and drain diffusion zones to be connected to these test pads. In the example, the semiconductor device is an MOS transistor T formed in a semiconductor substrate B and comprising a channel cc between two diffusion zones, source S and drain D, formed in the substrate, and a gate G (gate electrode and gate oxide, not differentiated in the figure). The device has two test pads p1 and p2, onto each of which a measurement tip of a measuring apparatus (not shown) will be placed. These pads are produced in the same surface plane, typically in a metallization level of the device, above the gate level of the transistor. They are, for example, metal platelets measuring a few tens of square micrometres. A connection line l1, which comprises the test pad p1, connects the two diffusion zones by corresponding contact pins. The gate G extends beyond the channel of the transistor, into a zone where it is insulated from the substrate by a thick dielectric i, allowing the gate to be connected to the other test pad p2 via a corresponding contact pin. The capacitances associated with the interconnection elements (test pads, interconnection line or contact pins) comprise in particular the following capacitances: the capacitance c4 between the gate contact pin of the pad p2 and the substrate; the capacitance c5 between the pad p2 and the substrate; the capacitance c6 between the connection line l1 and the substrate; the capacitance c7 between the pad p1 and the substrate; and the capacitance c8 between the two pads p1 and p2, which depends on the distance between the two pads. Referring to the example of the 45 nanometre technology node, the magnitude of each of the interconnection capacitances c5 and c7 induced by the test pads (p1 or p2), measuring 100 microns by 100 microns, is of the order of one picofarad. In practice, depending on the topology of the interconnection elements in relation to the substrate, a dispersion of the order of 10 percent is observed in the interconnection capacitances, particularly when these capacitances are formed with the insulation dielectric i for which the fabrication constraints are less compared with the constraints applying to the gate oxide.
FIG. 4 lastly illustrates the stray capacitances c1, c2, c3 associated with a measuring apparatus 3, which typically comprises a capacimeter and a handling device (“prober”). An arbitrary semiconductor device to be tested, referenced 1, is arranged in the conventional way on a substrate holder 2. The measuring apparatus 3 controls two measurement tips 4 and 5, which are applied onto the semiconductor device at two test points. The stray capacitances are the capacitances c1 and c2 between each tip and the substrate, and the stray capacitance c3 between two tips. Together, these stray capacitances may amount to a value of the order of one picofarad (10−12 farad). This value varies according to the configuration of the tips and their position with respect to the substrate holder.
For the advanced technological processes of interest to us, these various stray capacitances are of the order of magnitude of the capacitances to be measured.
Lastly, the measurements are further affected by the tolerance in the dimensions of the MOS structure. This is because, in order to facilitate technological comparisons, the value of the capacitance is conventionally calculated per unit area, which is to say, in the C(V) curves which are used, the measured capacitance is divided by the surface area of the MOS structure on which it has been recorded. The precision of the C(V) curves obtained then depends on the precision in the dimensions of the MOS structure, which may be evaluated at 12 percent of the nominal length of the technology in question according to the ITRS criteria (3σ dispersion).
Thus, the imprecisions in the dimensions of the transistors are added to the imprecisions associated with the stray capacitances. The reason is, as we have seen, that in reality a capacitance per unit area is calculated. A measured capacitance is therefore divided by the surface area of the transistor, that is to say the product of its width W by its length L, as defined in relation to FIG. 1.
In the invention, an attempt is therefore made to record reliably the C(V) curves of an MOS structure, i.e. a gate-oxide-semiconductor stack especially adapted for nanometric or subnanometric processes.
Solutions to the problems of precision in the capacitance measurements have already been sought. In particular, techniques are known which make it possible to circumvent the stray elements introduced by the measuring apparatus.
U.S. Pat. No. 7,069,525 discloses a method for characterization of MOS structures by means of ring oscillators using inverters which are connected at their outputs to different loads formed by MOS capacitances with different gate lengths. The various currents measured in the inverters are used to deduce the values of the load capacitances per inverter stage. Thus, the value of the gate oxide capacitance and the gate length dispersion are measured by differentiation. However, the method does not integrate the quantum effects which need to be considered in order to determine the gate oxide capacitance. Furthermore, the measurements do not take into account the switching current associated with each inverter, which varies as a function of the charge of the inverter.
Another known measurement technique for measuring the value of an interconnection capacitance, based on the inverter charge, makes it possible through dynamic measurement to eliminate the switching current as well as the interference introduced by the stray capacitances due to the probes being used and the measuring apparatus. This technique is described in the publication by B. W. McGaughy, J. C. Chen, D. Sylvester, C. Hu, “A Simple Method for On-Chip Sub-Femto Farad Interconnect Capacitance Measurement,” IEEE Electron Device Letters, Vol. 18, No. 1, pp. 21-23, January 1997. It is based on the use of two CMOS inverter, one charging an interconnection capacitance to be measured and the output of the other not being connected to any load. Suitably shaped control signals of the inverters make it possible to circumvent the switching current associated with each inverter.
U.S. Pat. No. 6,870,375 describes the use of a similar technique, again for measuring interconnection capacitances.
These interconnection capacitances are not of the same nature as the MOS capacitance. In particular, the interconnection capacitance does not have stray capacitances interfering with the measurement, and it has a constant value irrespective of the applied voltage.
Thus, although these techniques are highly suitable for measuring low interconnection capacitances with precision, they do not however make it possible to circumvent the other stray capacitances such as the stray capacitances belonging to the structure of the MOS transistor, or the problem of surface area precision. Moreover, we have seen that these stray capacitances are of the order of magnitude of the MOS capacitance which is intended to be measured with precision.